Semiconductor integrated circuit (IC) technology has experienced rapid progress including the continued minimization of feature sizes and the maximization of packing density. The minimization of feature size relies on improvement in photolithography and its ability to print smaller features or critical dimensions (CD), and further relies on the tuning of the lithography exposing process. However, in the advanced technology nodes, the processing window is getting smaller and the CD control has a limited margin. The existing method is not effective and may cause various issues, such as bridge or scum defects.
Therefore, a method and structures used the method are needed to address the above issues.